Job ID: JR0086037
Job Category: Engineering
Primary Location: Bangalore, KA IN
Job Type: College Grad
- Experience in ASIC Physical Design RTL to GDSII Implementation flow
- Experience with Logic synthesis, floor planning, power planning, placement, CTS, routing, timing sign-off, fill etc.
- Experience with Low power design closure (UPF based implementation) and associated sign-off (SG-LP/VCLP/Conformal)
- Knowledge of Timing .lib generation, Physical View Generation (LEF, GDS, CEL, FRAM, NDM etc.)
- Physical Verification (DRC/LVS/Density/Antenna etc.)
- Reliability Verification (EM/IR drop etc.)
- Well versed with TCL/Perl/Shell Scripting
- EDA tool knowledge: Design Compiler, ICC/ICC2, StarRC-XT, Primetime, ICV
Inside this Business Group
Bachelors or Masters Engineering Degree
The Core and Visual Computing Group (CVCG) is responsible for the architecture, design and development of the CPU core and visual technology IPs that are central to Intel's system-on-a-chip (SoC) products and key to our datacenter, client and Internet-of-Things (IOT) platforms. CVCG strives to lead the industry through continuous innovation and world class engineering.
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